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Vivado Design Suite Tutorial
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2014-06-20
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vivado hls示例教程.
Table of Contents
Revision History ................................................................................................................. 2
Chapter 1 Tutorial Description ................................................................6
Overview ............................................................................................................................ 6
Software Requirements...................................................................................................... 7
Hardware Requirements .................................................................................................... 7
Obtaining the Tutorial Designs .......................................................................................... 8
Preparing the Tutorial Design Files .................................................................................... 8
Chapter 2 High-Level Synthesis Introductory Tutorial ...........................9
Overview ............................................................................................................................ 9
Tutorial Design Description ............................................................................................... 9
HLS Lab 1: Creating a High-Level Synthesis Project .........................................................10
HLS: Lab 2 Using the Tcl Command Interface ...................................................................25
HLS: Lab 3: Using Solutions for Design Optimization .......................................................29
Chapter 3 C Validation ........................................................................... 41
Overview ...........................................................................................................................41
Tutorial Design Description ..............................................................................................41
Lab 1: C Validation and Debug..........................................................................................42
Lab 2: C Validation with ANSI C Arbitrary Precision Types...............................................50
Lab 3: C Validation with C++ Arbitrary Precision Types ...................................................55
Chapter 4 Interface Synthesis ................................................................ 60
Tutorial Design Description ..............................................................................................60
Interface Synthesis Lab 1: Block-Level I/O protocols........................................................61
Interface Synthesis Lab 2: Port I/O protocols ...................................................................69
Interface Synthesis Lab 3: Implementing Arrays as RTL Interfaces ..................................75
Interface Synthesis Lab 4: Implementing AXI Interfaces ..................................................90
Chapter 5 Arbitrary Precision Types...................................................... 99
Overview ...........................................................................................................................99
Arbitrary Precision: Lab 1 ................................................................................................ 100
Arbitray Precision: Lab 2 ................................................................................................. 105
Chapter 6 Design Analysis ................................................................... 111
Overview ......................................................................................................................... 111
Tutorial Design Description ............................................................................................ 111
Lab 1: Design Optimization ............................................................................................. 112
Chapter 7 Design Optimization ........................................................... 144
Overview ......................................................................................................................... 144
Tutorial Design Description ............................................................................................ 145
Lab 1: Optimizing a Matrix Multiplier............................................................................. 145
Lab 2: C Code Optimized for I/O Accesses ...................................................................... 164
Conclusion ....................................................................................................................... 167
Chapter 8 RTL Verification ................................................................... 168
Overview ......................................................................................................................... 168
Tutorial Design Description ............................................................................................ 168
Lab 1: RTL Verification and the C test bench .................................................................. 169
Lab 2: Viewing Trace Files in Vivado ............................................................................... 176
Lab 3: Viewing Trace Files in ModelSim .......................................................................... 180
Conclusion ....................................................................................................................... 184
Chapter 9 Using HLS IP in IP Integrator .............................................. 185
Overview ......................................................................................................................... 185
Tutorial Design Description ............................................................................................ 185
Lab 1: Integrate HLS IP with a Xilinx IP Block ................................................................. 186
Conclusion ....................................................................................................................... 209
Chapter 10 Using HLS IP in a Zynq Processor Design ........................ 210
Overview ......................................................................................................................... 210
Tutorial Design Description ............................................................................................ 210
Lab 1: Implement Vivado HLS IP on a Zynq Device ........................................................ 211
Chapter 11 Using HLS IP in System Generatorfor DSP....................... 237
Overview ......................................................................................................................... 237
Tutorial Design Description ............................................................................................ 237
Lab 1: Package HLS IP for System Generator .................................................................. 238
Conclusion ....................................................................................................................... 242
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