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FPGA的编译之二、Verilog HDL语言的FPGA快速
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2009-07-23
h1654155275.0032
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This manual describes the Verilog portion of Synopsys FPGA
Compiler II / FPGA Express application, part of the Synopsys suite
of synthesis tools. FPGA Compiler II / FPGA Express reads an RTL
Verilog HDL model of a discrete electronic system and synthesizes
this description into a gate-level netlist.
FPGA Compiler II / FPGA Express supports v1.6 of the Verilog
language. Deviations from the definition of the Verilog language are
explicitly noted. Constructs added in versions subsequent to Verilog
1.6 might not be supported. Aspects of the Verilog language that are
not supported are listed in Appendix B.
Compiler II / FPGA Express application, part of the Synopsys suite
of synthesis tools. FPGA Compiler II / FPGA Express reads an RTL
Verilog HDL model of a discrete electronic system and synthesizes
this description into a gate-level netlist.
FPGA Compiler II / FPGA Express supports v1.6 of the Verilog
language. Deviations from the definition of the Verilog language are
explicitly noted. Constructs added in versions subsequent to Verilog
1.6 might not be supported. Aspects of the Verilog language that are
not supported are listed in Appendix B.
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