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静止图像压缩标准JPEG IP核的设计与实现
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2009-08-14
刘敏
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本文介绍了基于静止图像压缩标准JPEG 基本模式的编码器软IP 核的设计与实现。本设计采用适于VLSI 实现的DCT 算法结构,单周期实现Huffman 编码,图像压缩过程流水线 实现, 达到高处理速率和高数据吞吐率。使用Design Compiler 在SMIC 0.18um CMOS 单元 库下综合，时钟频率可以达到125MHz，可处理每秒三十帧的1280*1024 SXGA 图像。本IP 核可以方便地集成到诸如数码相机、手机以及扫描仪等各种应用中。
关键词： JPEG; IP 核; ASIC; 流水线设计;
Abstract：The paper presents the design and implementation of a soft encoder IP based on the JPEG baseline image compression standard. The design adopted the DCT algorithm architecture which is efficient for VLSI implementation and could encode the Huffman code in a clock period, compress the image in pipelining and obtain high speed and throughput. Synthesized in Design Compiler with the SMIC 0.18um CMOS library , the result is up to 125MHZ frequency and could handle 30 frames per second of 1280*1024 SXGA images. This IP can be conveniently integrated into various application such as digital camera、cell phone、and color FAX, etc.
Key words：JPEG; IP Core; ASIC; Pipelining Desig
关键词： JPEG; IP 核; ASIC; 流水线设计;
Abstract：The paper presents the design and implementation of a soft encoder IP based on the JPEG baseline image compression standard. The design adopted the DCT algorithm architecture which is efficient for VLSI implementation and could encode the Huffman code in a clock period, compress the image in pipelining and obtain high speed and throughput. Synthesized in Design Compiler with the SMIC 0.18um CMOS library , the result is up to 125MHZ frequency and could handle 30 frames per second of 1280*1024 SXGA images. This IP can be conveniently integrated into various application such as digital camera、cell phone、and color FAX, etc.
Key words：JPEG; IP Core; ASIC; Pipelining Desig
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