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AD9243,pdf datasheet (Monolith
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格式:rar |
大小:554 |
2009-09-09
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The AD9243 utilizes a four-stage pipeline architecture with a
wideband input sample-and-hold amplifier (SHA) implemented
on a cost-effective CMOS process. Each stage of the pipeline,
excluding the last stage, consists of a low resolution flash A/D
connected to a switched capacitor DAC and interstage residue
amplifier (MDAC). The residue amplifier amplifies the difference
between the reconstructed DAC output and the flash input
for the next stage in the pipeline. One bit of redundancy is used
in each of the stages to facilitate digital correction of flash errors.
The last stage simply consists of a flash A/D.
wideband input sample-and-hold amplifier (SHA) implemented
on a cost-effective CMOS process. Each stage of the pipeline,
excluding the last stage, consists of a low resolution flash A/D
connected to a switched capacitor DAC and interstage residue
amplifier (MDAC). The residue amplifier amplifies the difference
between the reconstructed DAC output and the flash input
for the next stage in the pipeline. One bit of redundancy is used
in each of the stages to facilitate digital correction of flash errors.
The last stage simply consists of a flash A/D.
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