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DS90CR486,pdf datasheet (133MH
消耗积分:3 |
格式:rar |
大小:556 |
2009-10-14
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The DS90CR486 receiver converts eight Low Voltage Differential
Signaling (LVDS) data streams back into 48 bits of
LVCMOS/LVTTL data. Using a 133MHz clock, the data
throughput is 6.384Gbit/s (798Mbytes/s).
The multiplexing of data lines provides a substantial cable reduction.
Long distance parallel single-ended buses typically
require a ground wire per active signal (and have very limited
noise rejection capability). Thus, for a 48-bit wide data and
one clock, up to 98 conductors are required. With this Channel
Link chipset as few as 19 conductors (8 data pairs, 1 clock
pair and a minimum of one ground) are needed. This provides
an 80% reduction in interconnect width, which provides a system
cost savings, reduces connector physical size and cost,
and reduces shielding requirements due to the cables' smaller
form factor.
Signaling (LVDS) data streams back into 48 bits of
LVCMOS/LVTTL data. Using a 133MHz clock, the data
throughput is 6.384Gbit/s (798Mbytes/s).
The multiplexing of data lines provides a substantial cable reduction.
Long distance parallel single-ended buses typically
require a ground wire per active signal (and have very limited
noise rejection capability). Thus, for a 48-bit wide data and
one clock, up to 98 conductors are required. With this Channel
Link chipset as few as 19 conductors (8 data pairs, 1 clock
pair and a minimum of one ground) are needed. This provides
an 80% reduction in interconnect width, which provides a system
cost savings, reduces connector physical size and cost,
and reduces shielding requirements due to the cables' smaller
form factor.
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