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DS90UR907Q,pdf datasheet (5 -
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2009-10-14
陆军航空兵
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The DS90UR907Q converts FPD-Link to FPD-Link II. It translates
four LVDS data/control streams and one LVDS clock
pair (FPD-Link) into a high-speed serialized interface (FPDLink
II) over a single pair. This serial bus scheme greatly
eases system design by eliminating skew problems between
clock and data, reduces the number of connector pins, reduces
the interconnect size, weight, and cost, and overall
eases PCB layout. In addition, internal DC balanced encoding
is used to support AC-coupled interconnects.
The DS90UR907Q converts, balances and level shifts four
LVDS data/control streams, and embeds one LVDS clock pair
(FPD-Link) to a serial stream (FPD-Link II). Up to 24 bits of
RGB in the FPD-Link are serialized along with the three video
control signals.
four LVDS data/control streams and one LVDS clock
pair (FPD-Link) into a high-speed serialized interface (FPDLink
II) over a single pair. This serial bus scheme greatly
eases system design by eliminating skew problems between
clock and data, reduces the number of connector pins, reduces
the interconnect size, weight, and cost, and overall
eases PCB layout. In addition, internal DC balanced encoding
is used to support AC-coupled interconnects.
The DS90UR907Q converts, balances and level shifts four
LVDS data/control streams, and embeds one LVDS clock pair
(FPD-Link) to a serial stream (FPD-Link II). Up to 24 bits of
RGB in the FPD-Link are serialized along with the three video
control signals.
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