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DS90CF563/DS90CF564,pdf datash
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2009-10-14
h1708587244.0670
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The DS90CF563 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CF564 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 65 MHz, 18 bits of RGB data
and 3 bits of LCD timing and control data (FPLINE,
FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per
LVDS data channel. Using a 65 MHz clock, the data throughput
is 171 Mbytes per second. These devices are offered
with falling edge data strobes for convenient interface with a
variety of graphics and LCD panel controllers.
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CF564 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 65 MHz, 18 bits of RGB data
and 3 bits of LCD timing and control data (FPLINE,
FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per
LVDS data channel. Using a 65 MHz clock, the data throughput
is 171 Mbytes per second. These devices are offered
with falling edge data strobes for convenient interface with a
variety of graphics and LCD panel controllers.
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