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DS5240 pdf datasheet
消耗积分:3 |
格式:rar |
大小:555 |
2008-07-25
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The DS5240 is a high-speed 8051 compatible security processor with built-in system features designed to meet the
stringent FIPS-140 and Common Criteria validations required by banking regulations worldwide. Based on Dallas
Semiconductor’s battery-backed technology and fast-erase SRAM design, the DS5240 supports rapid “zeroization”
of secure information as a tamper response. Security-related features included on-chip are a fine-line top-level
metal grid to protect underlying circuitry from tampering, a Modulo Arithmetic Accelerator (MAA) using words up to
4096-bits in length for calculations including Public Key Infrastructure (PKI), a random number generator for key
creation, multiple on-chip environmental sensors to detect out-of-range conditions and generate a tamper
response, and a user-available DES engine for arbitrary data encryption. The user DES engine supports both
single and triple-DES (3DES) cryptographic operations. Other on-chip features include a true-time clock with alarm
interrupt/wake-up capability, a CRC-16/32 generator, a phase-locked loop (PLL) to simplify crystal selection and to
isolate internal chip clocks from external system clock, extended memory addressing of up to 4MB program and
4MB data and a 1kB stack (part of 5kB total SRAM) for high-level language support, circuitry to control battery
backing of certain internal circuits and external SRAM for storage of program and/or data, and sleep, idle and
power management modes for low power applications.
The DS5240’s comprehensive security measures create a trusted computing environment for the most sensitive
applications. These measures include an array of features specifically designed to resist known threats including
observation, analysis, and physical attack. They are designed such that a massive effort would be required to
obtain information about the contents of the chip (e.g., stored encryption keys) and/or external memory.
Furthermore, the “soft” nature of the DS5240 (SRAM storage) allows frequent modification of secure information,
either program or data.
stringent FIPS-140 and Common Criteria validations required by banking regulations worldwide. Based on Dallas
Semiconductor’s battery-backed technology and fast-erase SRAM design, the DS5240 supports rapid “zeroization”
of secure information as a tamper response. Security-related features included on-chip are a fine-line top-level
metal grid to protect underlying circuitry from tampering, a Modulo Arithmetic Accelerator (MAA) using words up to
4096-bits in length for calculations including Public Key Infrastructure (PKI), a random number generator for key
creation, multiple on-chip environmental sensors to detect out-of-range conditions and generate a tamper
response, and a user-available DES engine for arbitrary data encryption. The user DES engine supports both
single and triple-DES (3DES) cryptographic operations. Other on-chip features include a true-time clock with alarm
interrupt/wake-up capability, a CRC-16/32 generator, a phase-locked loop (PLL) to simplify crystal selection and to
isolate internal chip clocks from external system clock, extended memory addressing of up to 4MB program and
4MB data and a 1kB stack (part of 5kB total SRAM) for high-level language support, circuitry to control battery
backing of certain internal circuits and external SRAM for storage of program and/or data, and sleep, idle and
power management modes for low power applications.
The DS5240’s comprehensive security measures create a trusted computing environment for the most sensitive
applications. These measures include an array of features specifically designed to resist known threats including
observation, analysis, and physical attack. They are designed such that a massive effort would be required to
obtain information about the contents of the chip (e.g., stored encryption keys) and/or external memory.
Furthermore, the “soft” nature of the DS5240 (SRAM storage) allows frequent modification of secure information,
either program or data.
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