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PCI-X Initiator/Target Core pd
消耗积分:3 |
格式:rar |
大小:555 |
2008-08-01
刘艳
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The V6201 is a high-performance, technology independent,
synthesizable core that implements the PCI-X 1.0
Local Bus protocol for PCI-X initiator and target applications.
The core supports a wide variety of design implementations
and features an easy-to-use application
interface. The general use of the core in a system is
shown in Fig 1: V6201 Megacell in a Typical Application.
The V6201 Megacell supports transfer rates up to 1 GB
per second on a 64-bit, 133 MHz PCI-X bus and 528 MB
per second on a 64-bit, 66 MHz PCI-2.2 bus. This core is
partitioned into 4 major blocks PCIXbus_mux, Configuration
space, Target and Initiator as shown in Fig 2: V6201
Megacell I/O Diagram.
The PCIXbus_mux block multiplexes the initiator and target
address/data buses and control signals. It contains
four data paths in and out for both target and Initiator.
The four uni-directional paths are multiplexed inside the
core. All the data transfers are register-to-register. Since
there are only a few registers on each data path, loading
is reduced and false timing paths are eliminated.
The Configuration Space block holds type 0 configuration
space header in the first 64-bytes, next 64-bytes are
reserved for extended capabilities and remaining 128-
bytes are available for user application.
The Target and Initiator blocks provides a simplified, synchronous
target and initiator interface. The core is selectable
to operate in PCI2.2/PCI-X mode depending on the
reset conditions. The PCI bus width is configurable to 32
or 64 bit. The core automatically handles conversion of
32/64 bit regardless of the PCI bus width.
synthesizable core that implements the PCI-X 1.0
Local Bus protocol for PCI-X initiator and target applications.
The core supports a wide variety of design implementations
and features an easy-to-use application
interface. The general use of the core in a system is
shown in Fig 1: V6201 Megacell in a Typical Application.
The V6201 Megacell supports transfer rates up to 1 GB
per second on a 64-bit, 133 MHz PCI-X bus and 528 MB
per second on a 64-bit, 66 MHz PCI-2.2 bus. This core is
partitioned into 4 major blocks PCIXbus_mux, Configuration
space, Target and Initiator as shown in Fig 2: V6201
Megacell I/O Diagram.
The PCIXbus_mux block multiplexes the initiator and target
address/data buses and control signals. It contains
four data paths in and out for both target and Initiator.
The four uni-directional paths are multiplexed inside the
core. All the data transfers are register-to-register. Since
there are only a few registers on each data path, loading
is reduced and false timing paths are eliminated.
The Configuration Space block holds type 0 configuration
space header in the first 64-bytes, next 64-bytes are
reserved for extended capabilities and remaining 128-
bytes are available for user application.
The Target and Initiator blocks provides a simplified, synchronous
target and initiator interface. The core is selectable
to operate in PCI2.2/PCI-X mode depending on the
reset conditions. The PCI bus width is configurable to 32
or 64 bit. The core automatically handles conversion of
32/64 bit regardless of the PCI bus width.
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