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基于ASIC的H.264编码器设计及其ADSP验证策略
消耗积分:3 |
格式:rar |
大小:433 |
2009-12-15
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提出了H.264/AVC 硬件编码器的一种3 级流水结构，以此来提高硬件加速电路的
处理能力和利用效率。鉴于H.264 编码芯片验证的复杂性,还提出了一种基于ADSP-BF537
的新型多媒体SoC 验证平台，并讨论了如何利用BF537，对H.264 编码芯片进行全面、高效的软硬件协同验证。
【关键字】H.264 编码器；硬件加速器；ADSP-BF537；软硬件协同验证；SoC
【中图分类号】TN919.81 【文献标识码】A
Design of H.264 Video Encoder Based on ASIC and Its ADSP
Verification
WANG Yi，LIN Zu-lun
( Department of Optoelectronic Information, UESTC, Chengdu Sichuan 610054 China)
【Abstract】To improving the process capabilities and utilized efficiency of the hardware
accelerator, 3 pipeline architecture for H.264 video encoder is presented. This paper also
introduces a novel multimedia SoC verification platform based on ADSP-BF537 since the
verification of H.264 encoder chips is so complexity, and finally, How to using BF537 for
software/hardware co-verifing the H.264 encoder chip completely and effectively is discussed.
【Key words】H.264 video encoder; Hardware accelerator; ADSP-BF537; Software/hardware
co-verification; SoC
处理能力和利用效率。鉴于H.264 编码芯片验证的复杂性,还提出了一种基于ADSP-BF537
的新型多媒体SoC 验证平台，并讨论了如何利用BF537，对H.264 编码芯片进行全面、高效的软硬件协同验证。
【关键字】H.264 编码器；硬件加速器；ADSP-BF537；软硬件协同验证；SoC
【中图分类号】TN919.81 【文献标识码】A
Design of H.264 Video Encoder Based on ASIC and Its ADSP
Verification
WANG Yi，LIN Zu-lun
( Department of Optoelectronic Information, UESTC, Chengdu Sichuan 610054 China)
【Abstract】To improving the process capabilities and utilized efficiency of the hardware
accelerator, 3 pipeline architecture for H.264 video encoder is presented. This paper also
introduces a novel multimedia SoC verification platform based on ADSP-BF537 since the
verification of H.264 encoder chips is so complexity, and finally, How to using BF537 for
software/hardware co-verifing the H.264 encoder chip completely and effectively is discussed.
【Key words】H.264 video encoder; Hardware accelerator; ADSP-BF537; Software/hardware
co-verification; SoC
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