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74HC113 pdf datasheet
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2008-08-06
吴湛
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MM54HC113/MM74HC113
Dual J-K Flip-Flops with Preset
General Description
These high speed J-K Flip-Flops utilize advanced silicongate
CMOS technology to achieve the high noise immunity
and low power dissipation of standard CMOS integrated circuits.
These devices can drive 10 LS-TTL loads.
These flip-flops are edge sensitive to the clock input and
change state on the negative going transition of the clock
pulse. Each one has independent J, K, CLOCK, and PRESET
inputs and Q and Q inputs. PRESET is independent of
the clock and accomplished by a low level on the input.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
Features
Y Typical propagation delay: 16 ns
Y Wide operating voltage range: 2±6V
Y Low input current: 1 mA maximum
Y Low quiescent current: 40 mA (74HC Series)
Y High output drive: 10 LS-TTL loads
Dual J-K Flip-Flops with Preset
General Description
These high speed J-K Flip-Flops utilize advanced silicongate
CMOS technology to achieve the high noise immunity
and low power dissipation of standard CMOS integrated circuits.
These devices can drive 10 LS-TTL loads.
These flip-flops are edge sensitive to the clock input and
change state on the negative going transition of the clock
pulse. Each one has independent J, K, CLOCK, and PRESET
inputs and Q and Q inputs. PRESET is independent of
the clock and accomplished by a low level on the input.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
Features
Y Typical propagation delay: 16 ns
Y Wide operating voltage range: 2±6V
Y Low input current: 1 mA maximum
Y Low quiescent current: 40 mA (74HC Series)
Y High output drive: 10 LS-TTL loads
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