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74HC194 pdf datasheet
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大小:133 |
2008-08-06
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MM54HC194/MM74HC194
4-Bit Bidirectional Universal Shift Register
General Description
This 4-bit high speed bidirectional shift register utilizes advanced
silicon-gate CMOS technology to achieve the low
power consumption and high noise immunity of standard
CMOS integrated circuits, along with the ability to drive 10
LS-TTL loads. This device operates at speeds similar to the
equivalent low power Schottky part.
This bidirectional shift register is designed to incorporate
virtually all of the features a system designer may want in a
shift register. It features parallel inputs, parallel outputs,
right shift and left shift serial inputs, operating mode control
inputs, and a direct overriding clear line. The register has
four distinct modes of operation: PARALLEL (broadside)
LOAD; SHIFT RIGHT (in the direction QA toward QD);
SHIFT LEFT; INHIBIT CLOCK (do nothing).
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs, S0
and S1, high. The data are loaded into their respective flip
flops and appear at the outputs after the positive transition
of the CLOCK input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising
edge of the clock pulse when S0 is high and S1 is low.
Serial data for this mode is entered at the SHIFT RIGHT
data input. When S0 is low and S1 is high, data shifts left
synchronously and new data is entered at the SHIFT LEFT
serial input. Clocking of the flip flops is inhibited when both
mode control inputs are low. The mode control inputs
should be changed only when the CLOCK input is high.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
4-Bit Bidirectional Universal Shift Register
General Description
This 4-bit high speed bidirectional shift register utilizes advanced
silicon-gate CMOS technology to achieve the low
power consumption and high noise immunity of standard
CMOS integrated circuits, along with the ability to drive 10
LS-TTL loads. This device operates at speeds similar to the
equivalent low power Schottky part.
This bidirectional shift register is designed to incorporate
virtually all of the features a system designer may want in a
shift register. It features parallel inputs, parallel outputs,
right shift and left shift serial inputs, operating mode control
inputs, and a direct overriding clear line. The register has
four distinct modes of operation: PARALLEL (broadside)
LOAD; SHIFT RIGHT (in the direction QA toward QD);
SHIFT LEFT; INHIBIT CLOCK (do nothing).
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs, S0
and S1, high. The data are loaded into their respective flip
flops and appear at the outputs after the positive transition
of the CLOCK input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising
edge of the clock pulse when S0 is high and S1 is low.
Serial data for this mode is entered at the SHIFT RIGHT
data input. When S0 is low and S1 is high, data shifts left
synchronously and new data is entered at the SHIFT LEFT
serial input. Clocking of the flip flops is inhibited when both
mode control inputs are low. The mode control inputs
should be changed only when the CLOCK input is high.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
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