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74HC533 pdf datasheet
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2008-08-06
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MM54HC533/MM74HC533
TRI-STATEÉ Octal D-Type Latch
with Inverted Outputs
General Description
These high speed OCTAL D-TYPE LATCHES utilize advanced
silicon-gate CMOS technology. They possess the
high noise immunity and low power consumption of standard
CMOS integrated circuits, as well as the ability to drive
15 LS-TTL loads. Due to the large output drive capability
and the TRI-STATE feature, these devices are ideally suited
for interfacing with bus lines in a bus organized system.
When the LATCH ENABLE input is high, the data present
on the D inputs will appear inverted at the Q outputs. When
the LATCH ENABLE goes low, the inverted data will be retained
at the Q outputs until LATCH ENABLE returns high
again. When a high logic level is applied to the OUTPUT
CONTROL input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs
and the state of the storage elements.
The 54HC/74HC logic family is speed, function, and pin-out
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to VCC and ground.
Features
Y Typical propagation delay: 18 ns
Y Wide operating voltage range: 2 to 6 volts
Y Low input current: 1 mA maximum
Y Low quiescent current: 80 mA, maximum (74HC Series)
Y Compatible with bus-oriented systems
Y Output drive capability: 15 LS-TTL loads
TRI-STATEÉ Octal D-Type Latch
with Inverted Outputs
General Description
These high speed OCTAL D-TYPE LATCHES utilize advanced
silicon-gate CMOS technology. They possess the
high noise immunity and low power consumption of standard
CMOS integrated circuits, as well as the ability to drive
15 LS-TTL loads. Due to the large output drive capability
and the TRI-STATE feature, these devices are ideally suited
for interfacing with bus lines in a bus organized system.
When the LATCH ENABLE input is high, the data present
on the D inputs will appear inverted at the Q outputs. When
the LATCH ENABLE goes low, the inverted data will be retained
at the Q outputs until LATCH ENABLE returns high
again. When a high logic level is applied to the OUTPUT
CONTROL input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs
and the state of the storage elements.
The 54HC/74HC logic family is speed, function, and pin-out
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to VCC and ground.
Features
Y Typical propagation delay: 18 ns
Y Wide operating voltage range: 2 to 6 volts
Y Low input current: 1 mA maximum
Y Low quiescent current: 80 mA, maximum (74HC Series)
Y Compatible with bus-oriented systems
Y Output drive capability: 15 LS-TTL loads
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