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74HC540 pdf datasheet
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2008-08-06
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MM54HC534/MM74HC534
TRI-STATEÉ Octal D-Type Flip-Flop
with Inverted Outputs
General Description
These high speed Octal D-Type Flip-Flops utilize advanced
silicon-gate CMOS technology. They possess the high noise
immunity and low power consumption of standard CMOS
integrated circuits, as well as the ability to drive 15 LS-TTL
loads. Due to the large output drive capability and the TRISTATE
feature, these devices are ideally suited for interfacing
with bus lines in a bus organized system.
These devices are positive edge triggered flip-flops. Data at
the D inputs, meeting the setup and hold time requirements,
are inverted and transferred to the Q outputs on positive
going transitions of the CLOCK (CK) input. When a high
logic level is applied to the OUTPUT CONTROL (OC) input,
all outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the
storage elements.
The 54HC/74HC logic family is speed, function, and pinout
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to VCC and ground.
Features
Y Typical propagation delay: 23 ns
Y Wide operating voltage range: 2±6V
Y Low input current: 1 mA maximum
Y Low quiescent current: 80 mA maximum
Y Compatible with bus-oriented systems
Y Output drive capability: 15 LS-TTL loads
TRI-STATEÉ Octal D-Type Flip-Flop
with Inverted Outputs
General Description
These high speed Octal D-Type Flip-Flops utilize advanced
silicon-gate CMOS technology. They possess the high noise
immunity and low power consumption of standard CMOS
integrated circuits, as well as the ability to drive 15 LS-TTL
loads. Due to the large output drive capability and the TRISTATE
feature, these devices are ideally suited for interfacing
with bus lines in a bus organized system.
These devices are positive edge triggered flip-flops. Data at
the D inputs, meeting the setup and hold time requirements,
are inverted and transferred to the Q outputs on positive
going transitions of the CLOCK (CK) input. When a high
logic level is applied to the OUTPUT CONTROL (OC) input,
all outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the
storage elements.
The 54HC/74HC logic family is speed, function, and pinout
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to VCC and ground.
Features
Y Typical propagation delay: 23 ns
Y Wide operating voltage range: 2±6V
Y Low input current: 1 mA maximum
Y Low quiescent current: 80 mA maximum
Y Compatible with bus-oriented systems
Y Output drive capability: 15 LS-TTL loads
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