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74HC643 pdf datasheet
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2008-08-06
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MM54HC640/MM74HC640
Inverting Octal TRI-STATEÉ Transceiver
MM54HC643/MM74HC643
True-Inverting Octal TRI-STATE Transceiver
General Description
These TRI-STATE bi-directional buffers utilize advanced silicon-
gate CMOS technology, and are intended for two-way
asynchronous communication between data buses. They
have high drive current outputs which enable high speed
operation even when driving large bus capacitances. These
circuits possess the low power consumption and high noise
immunity usually associated with CMOS circuitry, yet have
speeds comparable to low power Schottky TTL circuits.
Each device has an active low enable G and a direction
control input, DIR. When DIR is high, data flows from the A
inputs to the B outputs. When DIR is low, data flows from
the B inputs to the A outputs. The MM54HC640/
MM74HC640 transfers inverted data from one bus to other
and the MM54HC643/MM74HC643 transfers inverted data
from the A bus to the B bus and true data from the B bus to
the A bus.
These devices can drive up to 15 LS-TTL Loads, and all
inputs are protected from damage due to static discharge by
diodes to VCC and ground.
Features
Y Typical propagation delay: 13 ns
Y Wide power supply range: 2±6V
Y Low quiescent current: 80 mA maximum (74 HC)
Y TRI-STATE outputs for connection to bus oriented
systems
Y High output drive: 6 mA (min)
Inverting Octal TRI-STATEÉ Transceiver
MM54HC643/MM74HC643
True-Inverting Octal TRI-STATE Transceiver
General Description
These TRI-STATE bi-directional buffers utilize advanced silicon-
gate CMOS technology, and are intended for two-way
asynchronous communication between data buses. They
have high drive current outputs which enable high speed
operation even when driving large bus capacitances. These
circuits possess the low power consumption and high noise
immunity usually associated with CMOS circuitry, yet have
speeds comparable to low power Schottky TTL circuits.
Each device has an active low enable G and a direction
control input, DIR. When DIR is high, data flows from the A
inputs to the B outputs. When DIR is low, data flows from
the B inputs to the A outputs. The MM54HC640/
MM74HC640 transfers inverted data from one bus to other
and the MM54HC643/MM74HC643 transfers inverted data
from the A bus to the B bus and true data from the B bus to
the A bus.
These devices can drive up to 15 LS-TTL Loads, and all
inputs are protected from damage due to static discharge by
diodes to VCC and ground.
Features
Y Typical propagation delay: 13 ns
Y Wide power supply range: 2±6V
Y Low quiescent current: 80 mA maximum (74 HC)
Y TRI-STATE outputs for connection to bus oriented
systems
Y High output drive: 6 mA (min)
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