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SLGU877 pdf datasheet (1.8V PL
消耗积分:3 |
格式:rar |
大小:444 |
2008-08-06
张丽
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The SLGU877 is a PLL based zero delay buffer designed for 1.7V to 1.9V VDD operating range. The differential
clock input pair (CLK/ CLK) is distributed to 10 differential output pairs (Y[0:9]/ Y[0:9]) and one differential
feedback pair (FBOUT/ FBOUT). All output pairs are controlled by: (CLK/ CLK) inputs, (FBIN/
FBIN) inputs, OS,OE inputs, and analog VDD supply pin (AVDD).
OS input is a program pin that must be tied to GND or VDD. With OS= high and OE driven low, all outputs
except for (FBOUT/ FBOUT) are disabled to low (LZ).
With OS= low and OE driven low, all outputs except for (Y7/ Y7, FBOUT/ FBOUT) are disabled to low (LZ).
It leaves (Y7/ Y7) free running in addition to (FBOUT/ FBOUT).
Setting both CLK and CLK to logic low is used to put the device in a low power state. The PLL is turned
off, input receivers disabled, and all clock outputs are disabled to low (LZ). The PLL, inputs, and outputs
will power-on again after (CLK/ CLK) inputs have re-started as a differential signal. For power-on, it is necessary
to wait the stabilization time (TL) for the PLL to achieve lock of the feedback input pair (FBIN/ FBIN)
to the clock input pair (CLK/ CLK).
When the AVDD pin is grounded, (CLK/ CLK) bypasses the PLL, and is presented to the output pairs. This
mode is intended for testing purposes.The CLK/CLK inputs should be activated after VDDQ/AVDD power.
The SLGU877 is optimized for minimum timing skews and tracks spread spectrum input clocking for EMI
reduction.
clock input pair (CLK/ CLK) is distributed to 10 differential output pairs (Y[0:9]/ Y[0:9]) and one differential
feedback pair (FBOUT/ FBOUT). All output pairs are controlled by: (CLK/ CLK) inputs, (FBIN/
FBIN) inputs, OS,OE inputs, and analog VDD supply pin (AVDD).
OS input is a program pin that must be tied to GND or VDD. With OS= high and OE driven low, all outputs
except for (FBOUT/ FBOUT) are disabled to low (LZ).
With OS= low and OE driven low, all outputs except for (Y7/ Y7, FBOUT/ FBOUT) are disabled to low (LZ).
It leaves (Y7/ Y7) free running in addition to (FBOUT/ FBOUT).
Setting both CLK and CLK to logic low is used to put the device in a low power state. The PLL is turned
off, input receivers disabled, and all clock outputs are disabled to low (LZ). The PLL, inputs, and outputs
will power-on again after (CLK/ CLK) inputs have re-started as a differential signal. For power-on, it is necessary
to wait the stabilization time (TL) for the PLL to achieve lock of the feedback input pair (FBIN/ FBIN)
to the clock input pair (CLK/ CLK).
When the AVDD pin is grounded, (CLK/ CLK) bypasses the PLL, and is presented to the output pairs. This
mode is intended for testing purposes.The CLK/CLK inputs should be activated after VDDQ/AVDD power.
The SLGU877 is optimized for minimum timing skews and tracks spread spectrum input clocking for EMI
reduction.
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