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MAX1219 pdf datasheet (1.8V, D
消耗积分:2 |
格式:rar |
大小:666 |
2008-10-09
20762
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The MAX1219 dual, monolithic, 12-bit, 210Msps analog-to-digital converter (ADC) provides outstanding dynamic performance up to a 250MHz input frequency. The device operates with conversion rates up to 210Msps while consuming only 800mW per channel.
At 210Msps and an input frequency of 200MHz, the MAX1219 achieves a 79dBc spurious-free dynamic range (SFDR) with excellent 65.5dB signal-to-noise ratio (SNR) at 200MHz. The SNR remains flat (within 3dB) for input tones up to 250MHz. This makes the MAX1219 ideal for wideband applications such as communications receivers, cable head-end receivers, and power-amplifier predistortion in cellular base-station transceivers.
The MAX1219 operates from a single 1.8V power supply. The analog inputs of each channel are designed for AC-coupled, differential or single-ended operation. The ADC also features a selectable on-chip divide-by-2 clock circuit that accepts clock frequencies as high as 420MHz and reduces the phase noise of the input clock source. A low-voltage differential signal (LVDS) sampling clock is recommended for best performance. The converter's digital outputs are LVDS compatible and the data format can be selected to be either two's complement or offset binary.
The MAX1219 is available in a 100-pin TQFP package with exposed paddle and is specified over the extended (-40°C to +85°C) temperature range. Refer to the MAX1218 (170Msps) and the MAX1217 (125Msps) data sheets for lower speed, pin-compatible devices.
At 210Msps and an input frequency of 200MHz, the MAX1219 achieves a 79dBc spurious-free dynamic range (SFDR) with excellent 65.5dB signal-to-noise ratio (SNR) at 200MHz. The SNR remains flat (within 3dB) for input tones up to 250MHz. This makes the MAX1219 ideal for wideband applications such as communications receivers, cable head-end receivers, and power-amplifier predistortion in cellular base-station transceivers.
The MAX1219 operates from a single 1.8V power supply. The analog inputs of each channel are designed for AC-coupled, differential or single-ended operation. The ADC also features a selectable on-chip divide-by-2 clock circuit that accepts clock frequencies as high as 420MHz and reduces the phase noise of the input clock source. A low-voltage differential signal (LVDS) sampling clock is recommended for best performance. The converter's digital outputs are LVDS compatible and the data format can be selected to be either two's complement or offset binary.
The MAX1219 is available in a 100-pin TQFP package with exposed paddle and is specified over the extended (-40°C to +85°C) temperature range. Refer to the MAX1218 (170Msps) and the MAX1217 (125Msps) data sheets for lower speed, pin-compatible devices.
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