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CADENCE SIP RF ARCHITECT
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2008-10-16
王传璧
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CADENCE SIP RF ARCHITECT
While system-in-package (SiP) design makes it possible to combine RF and analog
content on the same substrate, it presents a number of challenges. These include
designing and integrating RF/analog chips with substrate-level buried RF passive
devices as well as enabling top-level pre- and post-layout circuit simulation of the
entire SiP design. Cadence
SiP RF Architect provides the proven path between
analog design and simulation and SiP RF layout. It enables designers to create a
single, system-level, circuit simulation-ready schematic for RF/analog die, SiP
substrate, and packaged and embedded discretes.
While system-in-package (SiP) design makes it possible to combine RF and analog
content on the same substrate, it presents a number of challenges. These include
designing and integrating RF/analog chips with substrate-level buried RF passive
devices as well as enabling top-level pre- and post-layout circuit simulation of the
entire SiP design. Cadence
SiP RF Architect provides the proven path between
analog design and simulation and SiP RF layout. It enables designers to create a
single, system-level, circuit simulation-ready schematic for RF/analog die, SiP
substrate, and packaged and embedded discretes.
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