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SST89E564/SST89V564/SST89E554/
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2009-02-11
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SST89E564, SST89V564, SST89E554, and SST89V554
are members of the FlashFlex51 family of 8-bit microcontrollers.
The FlashFlex51 is a family of microcontroller products
designed and manufactured on the state-of-the-art Super-
Flash CMOS semiconductor process technology. The
device uses the same powerful instruction set and is pin-forpin
compatible with standard 8xC5x microcontroller devices.
The device comes with 72/40 KByte of on-chip flash
EEPROM program memory using SST’s patented and proprietary
CMOS SuperFlash EEPROM technology with the
SST’s field-enhancing, tunneling injector, split-gate memory
cells. The SuperFlash memory is partitioned into 2
independent program memory blocks. The primary Super-
Flash Block 0 occupies 64/32 KByte of internal program
memory space and the secondary SuperFlash Block 1
occupies 8 KByte of internal program memory space. The
8-KByte secondary SuperFlash block can be mapped to
the lowest location of the 64/32 KByte address space; it
can also be hidden from the program counter and used as
an independent EEPROM-like data memory. The flash
memory blocks can be programmed via a standard 87C5x
OTP EPROM programmer fitted with a special adapter and
firmware for SST’s device. During the power-on reset, the
device can be configured as a slave to an external host for
source code storage or as a master to an external host for
In-Application Programming (IAP) operation. The device is
designed to be programmed “In-System” and “In-Application”
on the printed circuit board for maximum flexibility. The
device is pre-programmed with an example of bootstrap
loader in the memory, demonstrating the initial user program
code loading or subsequent user code updating via
the “IAP” operation. An example of bootstrap loader is for
the user’s reference and convenience only. SST does not
guarantee the functionality or the usefulness of the sample
bootstrap loader. Chip-Erase or Block-Erase operations will
erase the pre-programmed sample code.
In addition to 72/40 KByte of SuperFlash EEPROM program
memory on-chip, the device can address up to 64
KByte of external program memory. In addition to 1024 x 8
bits of on-chip RAM, up to 64 KByte of external RAM can
be addressed.
SST’s highly reliable, patented SuperFlash technology and
memory cell architecture have a number of important
advantages for designing and manufacturing flash
EEPROMs. These advantages translate into significant
cost and reliability benefits for our customers.
are members of the FlashFlex51 family of 8-bit microcontrollers.
The FlashFlex51 is a family of microcontroller products
designed and manufactured on the state-of-the-art Super-
Flash CMOS semiconductor process technology. The
device uses the same powerful instruction set and is pin-forpin
compatible with standard 8xC5x microcontroller devices.
The device comes with 72/40 KByte of on-chip flash
EEPROM program memory using SST’s patented and proprietary
CMOS SuperFlash EEPROM technology with the
SST’s field-enhancing, tunneling injector, split-gate memory
cells. The SuperFlash memory is partitioned into 2
independent program memory blocks. The primary Super-
Flash Block 0 occupies 64/32 KByte of internal program
memory space and the secondary SuperFlash Block 1
occupies 8 KByte of internal program memory space. The
8-KByte secondary SuperFlash block can be mapped to
the lowest location of the 64/32 KByte address space; it
can also be hidden from the program counter and used as
an independent EEPROM-like data memory. The flash
memory blocks can be programmed via a standard 87C5x
OTP EPROM programmer fitted with a special adapter and
firmware for SST’s device. During the power-on reset, the
device can be configured as a slave to an external host for
source code storage or as a master to an external host for
In-Application Programming (IAP) operation. The device is
designed to be programmed “In-System” and “In-Application”
on the printed circuit board for maximum flexibility. The
device is pre-programmed with an example of bootstrap
loader in the memory, demonstrating the initial user program
code loading or subsequent user code updating via
the “IAP” operation. An example of bootstrap loader is for
the user’s reference and convenience only. SST does not
guarantee the functionality or the usefulness of the sample
bootstrap loader. Chip-Erase or Block-Erase operations will
erase the pre-programmed sample code.
In addition to 72/40 KByte of SuperFlash EEPROM program
memory on-chip, the device can address up to 64
KByte of external program memory. In addition to 1024 x 8
bits of on-chip RAM, up to 64 KByte of external RAM can
be addressed.
SST’s highly reliable, patented SuperFlash technology and
memory cell architecture have a number of important
advantages for designing and manufacturing flash
EEPROMs. These advantages translate into significant
cost and reliability benefits for our customers.
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