资料下载
×
Emulating a synchronous serial
消耗积分:2 |
格式:rar |
大小:333 |
2009-04-02
李敏
分享资料个
The C500 microcontroller family usually provides only one on-chip synchronous serial
channel (SSC). If a second SSC is required, an emulation of the missing interface may
help to avoid an external hardware solution with additional electronic components.
The solution presented in this paper and in the attached source files emulates the most
important SSC functions by using optimized SW routines with a performance up to 25
KBaud in Slave Mode with half duplex transmission and an overhead less than 60% at
SAB C513 with 12 MHz. Due to the implementation in C this performance is not the limit
of the chip. A pure implementation in assembler will result in a strong reduction of the
CPU load and therefore increase the maximum speed of the interface. In addition,
microcontrollers like the SAB C505 will speed up the interface by a factor of two because
of an optimized architecture compared with the SAB C513.
Moreover, this solution lays stress on using as few on-chip hardware resources as
possible. A more excessive consumption of those resources will result in a higher
maximum speed of the emulated interface.
Due to the restricted performance of an 8 bit microcontroller a pin compatible solution is
provided only; the internal register based programming interface is replaced by a set of
subroutine calls.
The attached source files also contain a test shell, which demonstrates how to exchange
information between an on-chip HW-SSC and the emulated SW-SSC via 5 external wires
in different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).
A table with load measurements is presented to give an indication for the fraction of CPU
performance required by software for emulating the SSC.
channel (SSC). If a second SSC is required, an emulation of the missing interface may
help to avoid an external hardware solution with additional electronic components.
The solution presented in this paper and in the attached source files emulates the most
important SSC functions by using optimized SW routines with a performance up to 25
KBaud in Slave Mode with half duplex transmission and an overhead less than 60% at
SAB C513 with 12 MHz. Due to the implementation in C this performance is not the limit
of the chip. A pure implementation in assembler will result in a strong reduction of the
CPU load and therefore increase the maximum speed of the interface. In addition,
microcontrollers like the SAB C505 will speed up the interface by a factor of two because
of an optimized architecture compared with the SAB C513.
Moreover, this solution lays stress on using as few on-chip hardware resources as
possible. A more excessive consumption of those resources will result in a higher
maximum speed of the emulated interface.
Due to the restricted performance of an 8 bit microcontroller a pin compatible solution is
provided only; the internal register based programming interface is replaced by a set of
subroutine calls.
The attached source files also contain a test shell, which demonstrates how to exchange
information between an on-chip HW-SSC and the emulated SW-SSC via 5 external wires
in different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).
A table with load measurements is presented to give an indication for the fraction of CPU
performance required by software for emulating the SSC.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
