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CD4099.pdf
消耗积分:10 |
格式:rar |
大小:122 |
2008-04-02
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The CD4099BC is an 8-bit addressable latch with three
address inputs (A0–A2), an active low enable input (E),
active high clear input (CL), a data input (D), and eight outputs
(Q0–Q7).
Data is entered into a particular bit in the latch when that bit
is addressed by the address inputs and the enable (E) is
LOW. Data entry is inhibited when enable (E) is HIGH.
When clear (CL) and enable (E) are HIGH, all outputs are
LOW. When clear (CL) is HIGH and enable (E) is LOW, the
channel demultiplexing occurs. The bit that is addressed
has an active output which follows the data input while all
unaddressed bits are held LOW. When operating in the
addressable latch mode (E = CL = LOW), changing more
than one bit of the address could impose a transient wrong
address. Therefore, this should only be done while in the
memory mode (E = HIGH, CL = LOW).
Features
Wide supply voltage range: 3.0V to 15V
High noise immunity: 0.45 VDD (typ.)
Low power TTL: fan out of 2 driving 74L
compatibility: or 1 driving 74LS
Serial to parallel capability
Storage register capability
Random (addressable) data entry
Active high demultiplexing capability
Common active high clear
address inputs (A0–A2), an active low enable input (E),
active high clear input (CL), a data input (D), and eight outputs
(Q0–Q7).
Data is entered into a particular bit in the latch when that bit
is addressed by the address inputs and the enable (E) is
LOW. Data entry is inhibited when enable (E) is HIGH.
When clear (CL) and enable (E) are HIGH, all outputs are
LOW. When clear (CL) is HIGH and enable (E) is LOW, the
channel demultiplexing occurs. The bit that is addressed
has an active output which follows the data input while all
unaddressed bits are held LOW. When operating in the
addressable latch mode (E = CL = LOW), changing more
than one bit of the address could impose a transient wrong
address. Therefore, this should only be done while in the
memory mode (E = HIGH, CL = LOW).
Features
Wide supply voltage range: 3.0V to 15V
High noise immunity: 0.45 VDD (typ.)
Low power TTL: fan out of 2 driving 74L
compatibility: or 1 driving 74LS
Serial to parallel capability
Storage register capability
Random (addressable) data entry
Active high demultiplexing capability
Common active high clear
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