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介绍8xC251SB与MCS-251微控制器的编程差异并通过
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大小:167 |
2009-06-24
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The MCS® 251 microcontrollers is Intel’s next generation MCS 51 microcontrollers. The MCS 251 first product, 8xC251SB is binary code and pin compatible with the existing 80C51 microcontrollers and its derivatives. With instruction pipeline and register based architecture, the 8xC251SB CPU executes most of the instructions in 1 state or 2 clocks period compared with 6 states or 12 clocks period in MCS 51 microcontrollers. Larger and more flexible memory
spaces are available with its 24-bit linear memory addressing capability. 8xC251SB has more programming capability. The instruction set has been enriched to provide 16-bit and 32-bit capability. 8xC251SB has more bit addressable space.
It has more addressing modes, register to register operations and improved data manipulation, accessing, and transfer capabilities. More control instructions are also available to optimize program flow.
1.0 INTRODUCTION.........4
2.0 8XC251SB CPU FEATURES...4
3.0 MEMORY ORGANIZATION.4
3.1 CODE AND DATA MEMORY SPACE5
3.2 REGISTER FILE .................7
3.3 SPECIAL FUNCTION REGISTER (SFR) ..............9
3.3.1 Program Counter (PC) .......10
3.3.2 Program Status Word (PSW).................10
3.3.3 Data Pointer (DPX).10
3.3.4 Stack Pointer (SPX) .10
4.0 ADDRESSING MODES.........10
4.1 REGISTER ADDRESSING ..11
4.2 IMMEDIATE ADDRESSING12
4.3 DIRECT ADDRESSING......12
4.4 INDIRECT ADDRESSING...12
4.5 DISPLACEMENT ADDRESSING.....13
4.6 RELATIVE ADDRESSING ..13
4.7 BIT ADDRESSING............13
5.0 INSTRUCTION SET...13
5.1 ARITHMETIC INSTRUCTIONS.......13
5.2 DATA TRANSFER INSTRUCTIONS.14
5.3 LOGICAL INSTRUCTIONS .15
5.4 BIT INSTRUCTIONS .........16
5.5 CONTROL INSTRUCTIONS 16
6.0 CONCLUSION............16
APPENDIX A: INSTRUCTION CYCLE IMPROVEMENT.................17
APPENDIX B: EXAMPLES OF NEW 8XC251SB ARITHMETIC INSTRUCTION........28
APPENDIX C: EXAMPLES OF NEW 8XC251SB DATA TRANSFER INSTRUCTION.32
APPENDIX D: EXAMPLES OF NEW 8XC251SB LOGICAL INSTRUCTION...............35
APPENDIX E: EXAMPLES OF NEW 8XC251SB CONTROL INSTRUCTION..............37
ADDITIONAL REFERENCES...38
spaces are available with its 24-bit linear memory addressing capability. 8xC251SB has more programming capability. The instruction set has been enriched to provide 16-bit and 32-bit capability. 8xC251SB has more bit addressable space.
It has more addressing modes, register to register operations and improved data manipulation, accessing, and transfer capabilities. More control instructions are also available to optimize program flow.
1.0 INTRODUCTION.........4
2.0 8XC251SB CPU FEATURES...4
3.0 MEMORY ORGANIZATION.4
3.1 CODE AND DATA MEMORY SPACE5
3.2 REGISTER FILE .................7
3.3 SPECIAL FUNCTION REGISTER (SFR) ..............9
3.3.1 Program Counter (PC) .......10
3.3.2 Program Status Word (PSW).................10
3.3.3 Data Pointer (DPX).10
3.3.4 Stack Pointer (SPX) .10
4.0 ADDRESSING MODES.........10
4.1 REGISTER ADDRESSING ..11
4.2 IMMEDIATE ADDRESSING12
4.3 DIRECT ADDRESSING......12
4.4 INDIRECT ADDRESSING...12
4.5 DISPLACEMENT ADDRESSING.....13
4.6 RELATIVE ADDRESSING ..13
4.7 BIT ADDRESSING............13
5.0 INSTRUCTION SET...13
5.1 ARITHMETIC INSTRUCTIONS.......13
5.2 DATA TRANSFER INSTRUCTIONS.14
5.3 LOGICAL INSTRUCTIONS .15
5.4 BIT INSTRUCTIONS .........16
5.5 CONTROL INSTRUCTIONS 16
6.0 CONCLUSION............16
APPENDIX A: INSTRUCTION CYCLE IMPROVEMENT.................17
APPENDIX B: EXAMPLES OF NEW 8XC251SB ARITHMETIC INSTRUCTION........28
APPENDIX C: EXAMPLES OF NEW 8XC251SB DATA TRANSFER INSTRUCTION.32
APPENDIX D: EXAMPLES OF NEW 8XC251SB LOGICAL INSTRUCTION...............35
APPENDIX E: EXAMPLES OF NEW 8XC251SB CONTROL INSTRUCTION..............37
ADDITIONAL REFERENCES...38
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