资料下载
×
系统内非易失性闪速存储器再编程的原理、软硬件注意事项及对80
消耗积分:5 |
格式:rar |
大小:616 |
2009-06-26
王飞云
分享资料个
1.0 INTRODUCTION 1
1.1 PROM Programmer vs
System-Processor Controlled
Programming 1
1.2 Information Download and
Upload 1
Version Updates (Download) 1
Data Acquisition (Upload) 1
2.0 DEVICE FEATURES AND ISW
APPLICATION
CONSIDERATIONS 2
2.1 Flash Memory Pinouts 2
2.2 Command Register
Architecture 4
Simplified Processor Interface 4
Command Register Reset 5
Data Protection on Power
Transitions 5
2.3 VPP Specifications 6
3.0 HARDWARE DESIGN FOR ISW 6
3.1 VPP Generation 6
3.1.1 Regulating Down from
Higher Voltage 6
3.1.2 Pumping 5V up to 12V 6
3.1.3 Absolute Data Protection Ð
VPP On/Off Control 7
3.1.4 Writes and Reads during
VPP Transitions 7
3.1.5 Other VPP Considerations 7
3.1.6 VPP Circuitry and Trace
Layout 8
3.2 Communications Ð Getting Data
to and from the Flash
Memory 8
CONTENTS PAGE
4.0 SOFTWARE DESIGN FOR ISW 8
4.1 System Integration Ð Boot Code
Requirements 8
4.1.1 ISW Flag Check 9
4.2 Communication Protocols and
Flash Memory ISW 9
4.3 Data Accumulation Software
Techniques 10
4.4 Reprogramming Routines 10
4.4.1 Quick-Erase Algorithm 10
Algorithm Timing Delays 10
High Performance Parallel
Device Erasure 11
4.4.2 Quick-Pulse Programming
Algorithm 12
Algorithm Timing Delays 12
High Performance Parallel
Device Programming 12
4.4.3 Pulse Width Timing
Techniques 13
Software Methods and
Examples 13
Hardware Methods 13
5.0 SYSTEM DESIGN EXAMPLE: AN
80C186 DESIGN 14
6.0 SUMMARY 15
1.1 PROM Programmer vs
System-Processor Controlled
Programming 1
1.2 Information Download and
Upload 1
Version Updates (Download) 1
Data Acquisition (Upload) 1
2.0 DEVICE FEATURES AND ISW
APPLICATION
CONSIDERATIONS 2
2.1 Flash Memory Pinouts 2
2.2 Command Register
Architecture 4
Simplified Processor Interface 4
Command Register Reset 5
Data Protection on Power
Transitions 5
2.3 VPP Specifications 6
3.0 HARDWARE DESIGN FOR ISW 6
3.1 VPP Generation 6
3.1.1 Regulating Down from
Higher Voltage 6
3.1.2 Pumping 5V up to 12V 6
3.1.3 Absolute Data Protection Ð
VPP On/Off Control 7
3.1.4 Writes and Reads during
VPP Transitions 7
3.1.5 Other VPP Considerations 7
3.1.6 VPP Circuitry and Trace
Layout 8
3.2 Communications Ð Getting Data
to and from the Flash
Memory 8
CONTENTS PAGE
4.0 SOFTWARE DESIGN FOR ISW 8
4.1 System Integration Ð Boot Code
Requirements 8
4.1.1 ISW Flag Check 9
4.2 Communication Protocols and
Flash Memory ISW 9
4.3 Data Accumulation Software
Techniques 10
4.4 Reprogramming Routines 10
4.4.1 Quick-Erase Algorithm 10
Algorithm Timing Delays 10
High Performance Parallel
Device Erasure 11
4.4.2 Quick-Pulse Programming
Algorithm 12
Algorithm Timing Delays 12
High Performance Parallel
Device Programming 12
4.4.3 Pulse Width Timing
Techniques 13
Software Methods and
Examples 13
Hardware Methods 13
5.0 SYSTEM DESIGN EXAMPLE: AN
80C186 DESIGN 14
6.0 SUMMARY 15
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
