资料下载
PCI总线仲裁参考设计Verilog代码
分享资料个
PCI总线仲裁参考设计，Quicklogic提供
This application note describes a fully PCI-compliant Master/Slave
interface. It utilizes the
PCI burst transfer mode for transfers at high speed, up to 67 MBytes per
second. Although it
is designed to interface the Seeq 80C300 Ethernet Data Link Controller
to the PCI bus, it can
be easily modified to interface with other peripherals. Data is transferred
between System
Memory and the Ethernet controller in bursts of eight using Master Mode
DMA. Internal
80C300 programming registers are mapped into host memory space and
are accessed using
slave mode.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
- 相关下载
- 相关文章
