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FFT Processor
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格式:rar |
大小:408 |
2009-07-27
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Chapter 1-Introduction to VHDL
1.1 Introduction 1
1.2 Advantages of VHDL over other Hardware…
Description Languages 1
1.3 VHDL : The Language… 2
1.3.1 Entity Declaration 3
1.3.2 Architecture Body 3
1.3.3 Configuration Declaration.. 7
1.3.4 Package… 8
1.3.5 Testbench 9
Chapter 2-High Level Design Flow. 10
2.1 HDL Capture 10
2.2 RTL Simulation… 10
2.3 VHDL Synthesis.. 12
2.4 Functional Gate Level Verification. 13
2.5 Place and Route... 13
2.6 Post Layout Timing Simulation.. 15
Chapter 3-Illustration of VHDL 16
3.1 The IEEE floating-point standard 16
3.2 The Addition Process 17
3.3 Hardware Implementation of Floating-Point Adder 19
3.3.1 Block Diagram of the Adder 19
3.3.2 The Subtractor Unit 20
3.3.3 The Swap Unit… 21
3.3.4 The Shifter Unit.. 22
3.3.5 The Summer Unit 23
3.3.6 The Normalize Unit. 23
3.3.7 The Control Unit. 24
3.3.8 The Testbench for the adder 28
Chapter 4- The Fourier Transform… 30
4.1 The Discrete Fourier Transform... 30
4.1.1 An Illustration 30
4.1.2 Types of Fourier Transforms. 31
4.1.3 Notation and Format of the Real DFT. 33
4.1.4 DFT Basis Functions 34
4.1.5 Analysis, Calculating the DFT. 37
4.2 The Fast Fourier Transform. 37
4.2.1 Comparison of Real DFT and Complex DFT. 38
4.2.2 How the FFT works 39
4.3 Synthesis, Calculating the Inverse DFT 42
4.4 Illustration of the DFT and IDFT in Matlab 44
Chapter 5-Architectural Design of the FFT Processor 46
5.1 Block Diagram of the FFT Processor 46
5.2 Butterfly Processing Element 48
5.3 Address Generation Unit. 50
5.3.1 Butterfly Generator 52
5.3.2 Stage Generator.. 52
5.3.3 Stage Done_IO Done Block. 52
5.3.4 IO-Address Generator… 53
5.3.5 Base Index Generator…. 53
5.3.6 The Shifters 54
5.3.7 ROM Address Generator... 54
5.4 Controller. 55
5.5 RAM and ROM... 55
Chapter 6-RTL Simulation of the FFT Processor. 56
Chapter 7-Synthesis of the FFT Processor.59
Chapter 8-Conclusion. 60
APPENDIX A-Code Listing 61
APPENDIX B-Synthesis Results... 101
References .112
1.1 Introduction 1
1.2 Advantages of VHDL over other Hardware…
Description Languages 1
1.3 VHDL : The Language… 2
1.3.1 Entity Declaration 3
1.3.2 Architecture Body 3
1.3.3 Configuration Declaration.. 7
1.3.4 Package… 8
1.3.5 Testbench 9
Chapter 2-High Level Design Flow. 10
2.1 HDL Capture 10
2.2 RTL Simulation… 10
2.3 VHDL Synthesis.. 12
2.4 Functional Gate Level Verification. 13
2.5 Place and Route... 13
2.6 Post Layout Timing Simulation.. 15
Chapter 3-Illustration of VHDL 16
3.1 The IEEE floating-point standard 16
3.2 The Addition Process 17
3.3 Hardware Implementation of Floating-Point Adder 19
3.3.1 Block Diagram of the Adder 19
3.3.2 The Subtractor Unit 20
3.3.3 The Swap Unit… 21
3.3.4 The Shifter Unit.. 22
3.3.5 The Summer Unit 23
3.3.6 The Normalize Unit. 23
3.3.7 The Control Unit. 24
3.3.8 The Testbench for the adder 28
Chapter 4- The Fourier Transform… 30
4.1 The Discrete Fourier Transform... 30
4.1.1 An Illustration 30
4.1.2 Types of Fourier Transforms. 31
4.1.3 Notation and Format of the Real DFT. 33
4.1.4 DFT Basis Functions 34
4.1.5 Analysis, Calculating the DFT. 37
4.2 The Fast Fourier Transform. 37
4.2.1 Comparison of Real DFT and Complex DFT. 38
4.2.2 How the FFT works 39
4.3 Synthesis, Calculating the Inverse DFT 42
4.4 Illustration of the DFT and IDFT in Matlab 44
Chapter 5-Architectural Design of the FFT Processor 46
5.1 Block Diagram of the FFT Processor 46
5.2 Butterfly Processing Element 48
5.3 Address Generation Unit. 50
5.3.1 Butterfly Generator 52
5.3.2 Stage Generator.. 52
5.3.3 Stage Done_IO Done Block. 52
5.3.4 IO-Address Generator… 53
5.3.5 Base Index Generator…. 53
5.3.6 The Shifters 54
5.3.7 ROM Address Generator... 54
5.4 Controller. 55
5.5 RAM and ROM... 55
Chapter 6-RTL Simulation of the FFT Processor. 56
Chapter 7-Synthesis of the FFT Processor.59
Chapter 8-Conclusion. 60
APPENDIX A-Code Listing 61
APPENDIX B-Synthesis Results... 101
References .112
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