资料下载
×
AD9240,pdf datasheet (Monolith
消耗积分:3 |
格式:rar |
大小:557 |
2009-09-09
overheat
分享资料个
The AD9240 uses a four-stage pipeline architecture with a
wideband input sample-and-hold amplifier (SHA) implemented
on a cost-effective CMOS process. Each stage of the pipeline,
excluding the last, consists of a low resolution flash A/D connected
to a switched capacitor DAC and interstage residue
amplifier (MDAC). The residue amplifier amplifies the difference
between the reconstructed DAC output and the flash input
for the next stage in the pipeline. One bit of redundancy is used
in each of the stages to facilitate digital correction of flash errors.
The last stage simply consists of a flash A/D.
wideband input sample-and-hold amplifier (SHA) implemented
on a cost-effective CMOS process. Each stage of the pipeline,
excluding the last, consists of a low resolution flash A/D connected
to a switched capacitor DAC and interstage residue
amplifier (MDAC). The residue amplifier amplifies the difference
between the reconstructed DAC output and the flash input
for the next stage in the pipeline. One bit of redundancy is used
in each of the stages to facilitate digital correction of flash errors.
The last stage simply consists of a flash A/D.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
