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DS90CR285/DS90CR286,pdf datash
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2009-10-14
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The DS90CR285 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted
in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are
sampled and transmitted. The DS90CR286 receiver converts
the LVDS data streams back into 28 bits of LVCMOS/
LVTTL data. At a transmit clock frequency of 66 MHz, 28 bits
of TTL data are transmitted at a rate of 462 Mbps per LVDS
data channel. Using a 66 MHz clock, the data throughput is
1.848 Gbit/s (231 Mbytes/s).
LVTTL data into four LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted
in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are
sampled and transmitted. The DS90CR286 receiver converts
the LVDS data streams back into 28 bits of LVCMOS/
LVTTL data. At a transmit clock frequency of 66 MHz, 28 bits
of TTL data are transmitted at a rate of 462 Mbps per LVDS
data channel. Using a 66 MHz clock, the data throughput is
1.848 Gbit/s (231 Mbytes/s).
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