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AD6620,pdf datasheet (67 MSPS
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The AD6620 is a digital receiver with four cascaded signalprocessing
elements: a frequency translator, two fixedcoefficient
decimating filters, and a programmable coefficient
decimating filter. All inputs are 3.3 V LVCMOS compatible.
All outputs are LVCMOS and 5 V TTL compatible.
As ADCs achieve higher sampling rates and dynamic range, it
becomes increasingly attractive to accomplish the final IF stage
of a receiver in the digital domain. Digital IF Processing is less
expensive, easier to manufacture, more accurate, and more
flexible than a comparable highly selective analog stage.
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