资料下载
旋风VE加速杉木直接建在存储器存取的例子
563352763
分享资料个
Hardware Specifications This design makes use of several peripherals on the Cyclone V E FPGA Development Kit as well as several IP components. A full list is below： Clock source Interval timers Performance counter unit JTAG UART Button/LED PIO （implemented in the Qsys design， but not used in this example） Custom FIR-DMA （described in the “Theory of Operation” section of this document） Avalon-MM Pipeline Bridges Avalon-MM Clock Crossing Bridges Nios II Classic Processor Tri-State Conduit Bridge Tri-State Conduit Pin Sharer Generic Tri-State Controller （for SSRAM and flash memory， although flash memory is not used in this example） Clock Bridges DDR3 SDRAM Controller with Uniphy Altera PLL On-Chip RAM This design was implemented in Quartus II 15.0. A block diagram is below. Note that this block diagram is highly simplified and leaves out several peripherals and intermediate pipelining bridges. It is meant to highlight the most “important” parts of the hardware and how they are connected. A more detailed block diagram of the Custom FIR DMA block is included in the “Theory of Operation” section of this document.
Theory of Operation This design example implements a FIR filter with built-in direct memory access on a Cyclone V E FPGA Development Kit. The finite impulse response （FIR） filter is a common algorithm used in digital signal processing （DSP） systems. In this example， a FIR filter has been integrated into a single Qsys component containing Avalon® Memory-Mapped （Avalon-MM） read and write masters. The read master is responsible for supplying the filter with input data （from the SSRAM in this example）， while the write master is responsible for writing the filter response back to memory （the DDR3 SDRAM in this example）。 Since the filter has Avalon mastering capabilities， you do not need to use a separate direct memory access （DMA） engine to accomplish the filter operation. Below is a diagram of the Custom FIR DMA Qsys component.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
- 相关下载
- 相关文章
