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DDR2_DDR3_SDRAM，PCB布线规则指导
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DDR2 usage is common today with a push towards higher speeds such as 800 Mbps ［1］ and more recently，
1066 Mbps. DDR3 ［2］ targets a data rate of 1600 Mbps. From a PCB implementation standpoint， a primary
requirement is delay matching which is dictated by the timing requirement. This brings into it a number of related
factors that affect waveform integrity and delay. These factors are interdependent， but where a distinction can
be made， they can be termed PCB layer stackup and impedance， interconnect topologies， delay matching， cross
talk， PI and timing. Cadence ALLEGRO™SI-230 and Ansoft’s HFSS™ are used in all computations.
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