资料下载
×
74HC107 pdf datasheet
消耗积分:3 |
格式:rar |
大小:133 |
2008-08-06
吴湛
分享资料个
MM54HC107/MM74HC107
Dual J-K Flip-Flops with Clear
General Description
These J-K Flip-Flops utilize advanced silicon-gate CMOS
technology to achieve the high noise immunity and low power
dissipation of standard CMOS integrated circuits. These
devices can drive 10 LS-TTL loads.
These flip-flops are edge sensitive to the clock input and
change state on the negative going transition of the clock
pulse. Each one has independent J, K, CLOCK, and CLEAR
inputs and Q and Q outputs. CLEAR is independent of the
clock and accomplished by a low level on the input.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
Dual J-K Flip-Flops with Clear
General Description
These J-K Flip-Flops utilize advanced silicon-gate CMOS
technology to achieve the high noise immunity and low power
dissipation of standard CMOS integrated circuits. These
devices can drive 10 LS-TTL loads.
These flip-flops are edge sensitive to the clock input and
change state on the negative going transition of the clock
pulse. Each one has independent J, K, CLOCK, and CLEAR
inputs and Q and Q outputs. CLEAR is independent of the
clock and accomplished by a low level on the input.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
