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74HC109A pdf datasheet
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2008-08-06
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MM54HC109A/MM74HC109A
Dual J-K Flip-Flops with Preset and Clear
General Description
These J-K FLIP-FLOPS utilize advanced silicon-gate CMOS
technology to achieve the low power consumption and high
noise immunity of standard CMOS integrated circuits, along
with the ability to drive 10 LS-TTL loads.
Each flip flop has independent J, K PRESET, CLEAR and
CLOCK inputs and Q and Q outputs. These devices are
edge sensitive to the clock input and change state on the
positive going transition of the clock pulse. Clear and preset
are independent of the clock and accomplished by a low
logic level on the corresponding input.
Dual J-K Flip-Flops with Preset and Clear
General Description
These J-K FLIP-FLOPS utilize advanced silicon-gate CMOS
technology to achieve the low power consumption and high
noise immunity of standard CMOS integrated circuits, along
with the ability to drive 10 LS-TTL loads.
Each flip flop has independent J, K PRESET, CLEAR and
CLOCK inputs and Q and Q outputs. These devices are
edge sensitive to the clock input and change state on the
positive going transition of the clock pulse. Clear and preset
are independent of the clock and accomplished by a low
logic level on the corresponding input.
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