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74HC157 pdf datasheet
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大小:133 |
2008-08-06
吴湛
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MM54HC157/MM74HC157 Quad 2-Input Multiplexer
MM54HC158/MM74HC158 Quad 2-Input Multiplexer
(Inverted Output)
General Description
These high speed Quad 2-to-1 Line data selector/Multiplexers
utilize advanced silicon-gate CMOS technology. They
possess the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the
ability to drive 10 LS-TTL loads.
These devices each consist of four 2-input digital multiplexers
with common select and STROBE inputs. On the
MM54HC157/MM74HC157, when the STROBE input is at
logical ``0'' the four outputs assume the values as selected
from the inputs. When the STROBE input is at a logical ``1''
the outputs assume logical ``0''. The MM54HC158/
MM74HC158 operates in the same manner, except that its
outputs are inverted. Select decoding is done internally resulting
in a single select input only. If enabled, the select
input determines whether the A or B inputs get routed to
their corresponding Y outputs.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
Features
Y Typical propagation delay: 14 ns data to any output
Y Wide power supply range: 2±6V
Y Low power supply quiescent current: 80 mA maximum
(74HC Series)
Y Fan-out of 10 LS-TTL loads
Y Low input current: 1 mA maximum
MM54HC158/MM74HC158 Quad 2-Input Multiplexer
(Inverted Output)
General Description
These high speed Quad 2-to-1 Line data selector/Multiplexers
utilize advanced silicon-gate CMOS technology. They
possess the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the
ability to drive 10 LS-TTL loads.
These devices each consist of four 2-input digital multiplexers
with common select and STROBE inputs. On the
MM54HC157/MM74HC157, when the STROBE input is at
logical ``0'' the four outputs assume the values as selected
from the inputs. When the STROBE input is at a logical ``1''
the outputs assume logical ``0''. The MM54HC158/
MM74HC158 operates in the same manner, except that its
outputs are inverted. Select decoding is done internally resulting
in a single select input only. If enabled, the select
input determines whether the A or B inputs get routed to
their corresponding Y outputs.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
Features
Y Typical propagation delay: 14 ns data to any output
Y Wide power supply range: 2±6V
Y Low power supply quiescent current: 80 mA maximum
(74HC Series)
Y Fan-out of 10 LS-TTL loads
Y Low input current: 1 mA maximum
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