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74HC173 pdf datasheet
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2008-08-06
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MM54HC173/MM74HC173
TRI-STATEÉ Quad D Flip-Flop
General Description
The MM54HC173/MM74HC173 is a high speed TRI-STATE
QUAD D TYPE FLIP-FLOP that utilizes advanced silicongate
CMOS technology. It possesses the low power consumption
and high noise immunity of standard CMOS integrated
circuits, and can operate at speeds comparable to
the equivalent low power Schottky device. The outputs are
buffered, allowing this circuit to drive 15 LS-TTL loads. The
large output drive capability and TRI-STATE feature make
this part ideally suited for interfacing with bus lines in a bus
oriented system.
The four D TYPE FLIP-FLOPS operate synchronously from
a common clock. The TRI-STATE outputs allow the device
to be used in bus organized systems. The outputs are
placed in the TRI-STATE mode when either of the two output
disable pins are in the logic ``1'' level. The input disable
allows the flip-flops to remain in their present states without
having to disrupt the clock. If either of the 2 input disables
are taken to a logic ``1'' level, the Q outputs are fed back to
the inputs, forcing the flip flops to remain in the same state.
Clearing is enabled by taking the CLEAR input to a logic ``1''
level. The data outputs change state on the positive going
edge of the clock.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
TRI-STATEÉ Quad D Flip-Flop
General Description
The MM54HC173/MM74HC173 is a high speed TRI-STATE
QUAD D TYPE FLIP-FLOP that utilizes advanced silicongate
CMOS technology. It possesses the low power consumption
and high noise immunity of standard CMOS integrated
circuits, and can operate at speeds comparable to
the equivalent low power Schottky device. The outputs are
buffered, allowing this circuit to drive 15 LS-TTL loads. The
large output drive capability and TRI-STATE feature make
this part ideally suited for interfacing with bus lines in a bus
oriented system.
The four D TYPE FLIP-FLOPS operate synchronously from
a common clock. The TRI-STATE outputs allow the device
to be used in bus organized systems. The outputs are
placed in the TRI-STATE mode when either of the two output
disable pins are in the logic ``1'' level. The input disable
allows the flip-flops to remain in their present states without
having to disrupt the clock. If either of the 2 input disables
are taken to a logic ``1'' level, the Q outputs are fed back to
the inputs, forcing the flip flops to remain in the same state.
Clearing is enabled by taking the CLEAR input to a logic ``1''
level. The data outputs change state on the positive going
edge of the clock.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
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