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Calibre在IC设计版图中实现快速的模式匹配
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Human beings are visual people. From the earliest moments of our life, visual patterns are the dominant way we learn
about our world. Throughout our lifespan, we react more strongly to visual stimuli than any other. Even when we
speak different languages, we can communicate basic ideas via pictographs with perfect understanding.
IC layouts are visual in nature—any engineer who looks at a layout can instantly recognize transistors and wires and
vias—yet we have always defined them with an esoteric textual scripting language. We define layout features by
describing in text how wide and tall and long they are. We enhance these definitions by specifying the distances
allowed (or not allowed) between features. This text-based, one-dimensional approach worked well enough for a fairly
long time, but words have finally begun to fail us.
At today’s nanometer nodes, especially at 45 nm and below, we’re no longer defining relatively simple, onedimensional
length and width types of measurements. Lithography and manufacturing limitations combined with
performance requirements expand the radius of influence within a design layout, so that we now find ourselves trying
to describe an increasing set of combined features that are all interdependent, and sometimes multi-dimensional.
Some configurations are so complex that they simply cannot be accurately (or practically) described with existing
scripting language
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