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基于FPGA的NoC验证平台的构建
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2011-01-04
王芳
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针对基于软件仿真片上网络NoC（Network on Chip）效率低的问题，提出基于FPGA的NoC验证平台构建方案。该平台集成可重用的流量产生器TG（Traffic Generation）,流量接收器TR（Traffic Receiver）以及NoC软件，用于对NoC原型系统进行功能验证和性能评估。实际设计一个多核NoC，并用该平台对其进行FPGA验证，结果表明该平台的验证速度比软件仿真提高16000倍以上，并能对多种不同结构、路由算法、流控策略的NoC进行功能验证和性能评估。
- Abstract:
- To solve the problem of Network on Chip（NoC）low efficiency based on software simulation,a FPGA based valida-tion platform construction scheme for Network on Chip（NoC）was proposed.This platform intergrates reusable modules of a traffic generation（TG）,a traffic receiver（TR）and a NoC software,which are used to accomplish the function validation and performance evaluation.A NoC comprises many switching nodes was designed,and the NoC was validated by this plat-form.The experimental result shows that the speed of this platform reaches over16000times faster than software simulation;meanwhile,it can work on NoC which has different topology structure,routing algorithm and flow control strategy.
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