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DS90C032B,pdf datasheet (LVDS
消耗积分:3 |
格式:rar |
大小:557 |
2009-10-13
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TheDS90C032B is a quad CMOS differential line receiver
designed for applications requiring ultra low power dissipation
and high data rates. The device is designed to support
data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
TheDS90C032B accepts low voltage (350 mV) differential
input signals and translates them to CMOS (TTL compatible)
output levels. The receiver supports a TRI-STATE® function
that may be used to multiplex outputs. The receiver also
supports OPEN Failsafe and terminated (100Ω) input Failsafe
with the addition of external failsafe biasing. Receiver
output will be HIGH for both Failsafe conditions.
designed for applications requiring ultra low power dissipation
and high data rates. The device is designed to support
data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
TheDS90C032B accepts low voltage (350 mV) differential
input signals and translates them to CMOS (TTL compatible)
output levels. The receiver supports a TRI-STATE® function
that may be used to multiplex outputs. The receiver also
supports OPEN Failsafe and terminated (100Ω) input Failsafe
with the addition of external failsafe biasing. Receiver
output will be HIGH for both Failsafe conditions.
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