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LMH0346,pdf datasheet (3 Gbps
消耗积分:3 |
格式:rar |
大小:556 |
2009-10-14
李娜
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The LMH0346 3 Gbps HD/SD SDI Reclocker retimes serial
digital video data conforming to the SMPTE 424M, SMPTE
292M, and SMPTE 259M (C) standards. The LMH0346 operates
at serial data rates of 270 Mbps, 1.483 Gbps, 1.485
Gbps, 2.967 Gbps, and 2.97 Gbps. The LMH0346 supports
DVB-ASI operation at 270 Mbps.
The LMH0346 automatically detects the incoming data rate
and adjusts itself to retime the incoming data to suppress accumulated
jitter. The LMH0346 recovers the serial data-rate
clock and optionally provides it as an output. The LMH0346
has two differential serial data outputs; the second output may
be selected as a low-jitter, data-rate clock output. Controls
and indicators are: serial clock or second serial data output
select, manual rate select input, SD/HD rate indicator output,
lock detect output, auto/manual data bypass and output mute.
The serial data inputs, outputs, and serial clock outputs are
differential LVPECL compatible. The CML serial data and serial
clock outputs are suitable for driving 100Ω differentially
terminated networks. The control logic inputs and outputs are
LVCMOS compatible.
digital video data conforming to the SMPTE 424M, SMPTE
292M, and SMPTE 259M (C) standards. The LMH0346 operates
at serial data rates of 270 Mbps, 1.483 Gbps, 1.485
Gbps, 2.967 Gbps, and 2.97 Gbps. The LMH0346 supports
DVB-ASI operation at 270 Mbps.
The LMH0346 automatically detects the incoming data rate
and adjusts itself to retime the incoming data to suppress accumulated
jitter. The LMH0346 recovers the serial data-rate
clock and optionally provides it as an output. The LMH0346
has two differential serial data outputs; the second output may
be selected as a low-jitter, data-rate clock output. Controls
and indicators are: serial clock or second serial data output
select, manual rate select input, SD/HD rate indicator output,
lock detect output, auto/manual data bypass and output mute.
The serial data inputs, outputs, and serial clock outputs are
differential LVPECL compatible. The CML serial data and serial
clock outputs are suitable for driving 100Ω differentially
terminated networks. The control logic inputs and outputs are
LVCMOS compatible.
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