// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:51:50 $
//###########################################################################
//
// FILE: DSP2833x_Adc.h
//
// TITLE: DSP2833x Device ADC Register Definitions.
//
//###########################################################################
// $TI Release: DSP2833x Header Files V1.01 $
// $Release Date: September 26, 2007 $
//###########################################################################
#ifndef DSP2833x_ADC_H
#define DSP2833x_ADC_H
#ifdef __cplusplus
extern “C” {
#endif
//---------------------------------------------------------------------------
// ADC Individual Register Bit Definitions:
struct ADCTRL1_BITS { // bits description
Uint16 rsvd1:4; // 3:0 reserved
Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode
Uint16 SEQ_OVRD:1; // 5 Sequencer override
Uint16 CONT_RUN:1; // 6 Continuous run
Uint16 CPS:1; // 7 ADC core clock pre-scalar
Uint16 ACQ_PS:4; // 11:8 Acquisition window size
Uint16 SUSMOD:2; // 13:12 Emulation suspend mode
Uint16 RESET:1; // 14 ADC reset
Uint16 rsvd2:1; // 15 reserved
};
union ADCTRL1_REG {
Uint16 all;
struct ADCTRL1_BITS bit;
};
struct ADCTRL2_BITS { // bits description
Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2
Uint16 rsvd1:1; // 1 reserved
Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode
Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable
Uint16 rsvd2:1; // 4 reserved
Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2
Uint16 RST_SEQ2:1; // 6 Reset SEQ2
Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1
Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1
Uint16 rsvd3:1; // 9 reserved
Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode
Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable
Uint16 rsvd4:1; // 12 reserved
Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1
Uint16 RST_SEQ1:1; // 14 Restart sequencer 1
Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable
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