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EE241 Advanced Digital Integrated Circuits Lecture27.28
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Motivation behind Subthreshold SRAM Operation：
• Large area of chip devoted to SRAM Cache
• SRAM supply voltage needs to scale with logic supply voltage
• Reduce leakage by operating at DRV during hold
• Reduce active power consumption
Impediments to Subthreshold SRAM Operation
• Supply voltage scaling degrades cell stability
• Scaling increases sensitivity to process variations
– Variation induced local asymmetry， degraded SNM
– Spread in SNM over the whole SRAM array
• Impact of soft errors more significant at lower supply voltages
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