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74HC193 pdf datasheet
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2008-08-06
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MM54HC192/MM74HC192
Synchronous Decade Up/Down Counters
MM54HC193/MM74HC193
Synchronous Binary Up/Down Counters
General Description
These high speed synchronous counters utilize advanced
silicon-gate CMOS technology to achieve the high noise immunity
and low power consumption of CMOS technology,
along with the speeds of low power Schottky TTL. The
MM54HC192/MM74HC192 is a decade counter, and the
MM54HC193/MM74HC193 is a binary counter. Both counters
have two separate clock inputs, an UP COUNT input
and a DOWN COUNT input. All outputs of the flip-flops are
simultaneously triggered on the low to high transition of either
clock while the other input is held high. The direction of
counting is determined by which input is clocked.
These counters may be preset by entering the desired data
on the DATA A, DATA B, DATA C, and DATA D inputs.
When the LOAD input is taken low the data is loaded independently
of either clock input. This feature allows the counters
to be used as divide-by-n counters by modifying the
count length with the preset inputs.
In addition both counters can also be cleared. This is accomplished
by inputting a high on the CLEAR input. All 4
internal stages are set to a low level independently of either
COUNT input.
Both a BORROW and CARRY output are provided to enable
cascading of both up and down counting functions. The
BORROW output produces a negative going pulse when the
counter underflows and the CARRY outputs a pulse when
the counter overflows. The counters can be cascaded by
connecting the CARRY and BORROW outputs of one device
to the COUNT UP and COUNT DOWN inputs, respectively,
of the next device.
All inputs are protected from damage due to static discharge
by diodes to VCC and ground.
Synchronous Decade Up/Down Counters
MM54HC193/MM74HC193
Synchronous Binary Up/Down Counters
General Description
These high speed synchronous counters utilize advanced
silicon-gate CMOS technology to achieve the high noise immunity
and low power consumption of CMOS technology,
along with the speeds of low power Schottky TTL. The
MM54HC192/MM74HC192 is a decade counter, and the
MM54HC193/MM74HC193 is a binary counter. Both counters
have two separate clock inputs, an UP COUNT input
and a DOWN COUNT input. All outputs of the flip-flops are
simultaneously triggered on the low to high transition of either
clock while the other input is held high. The direction of
counting is determined by which input is clocked.
These counters may be preset by entering the desired data
on the DATA A, DATA B, DATA C, and DATA D inputs.
When the LOAD input is taken low the data is loaded independently
of either clock input. This feature allows the counters
to be used as divide-by-n counters by modifying the
count length with the preset inputs.
In addition both counters can also be cleared. This is accomplished
by inputting a high on the CLEAR input. All 4
internal stages are set to a low level independently of either
COUNT input.
Both a BORROW and CARRY output are provided to enable
cascading of both up and down counting functions. The
BORROW output produces a negative going pulse when the
counter underflows and the CARRY outputs a pulse when
the counter overflows. The counters can be cascaded by
connecting the CARRY and BORROW outputs of one device
to the COUNT UP and COUNT DOWN inputs, respectively,
of the next device.
All inputs are protected from damage due to static discharge
by diodes to VCC and ground.
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