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2008-04-02
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select gate. Low power and high noise margin over a wide
voltage range is possible through implementation of N- and
P-channel enhancement mode transistors. These complementary
MOS (CMOS) transistors provide the building
blocks for the 4 “AND-OR select” gate configurations, each
consisting of two 2-input AND gates driving a single 2-input
OR gate. Selection is accomplished by control bits KA and
KB. All inputs are protected against static discharge damage.
Features
Wide supply voltage range: 3.0V to 15V
High noise immunity: 0.45 VDD (typ.)
Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
Applications
• AND-OR select gating
• Shift-right/shift-left registers
• True/complement selection
• AND/OR/EXCLUSIVE-OR selection
voltage range is possible through implementation of N- and
P-channel enhancement mode transistors. These complementary
MOS (CMOS) transistors provide the building
blocks for the 4 “AND-OR select” gate configurations, each
consisting of two 2-input AND gates driving a single 2-input
OR gate. Selection is accomplished by control bits KA and
KB. All inputs are protected against static discharge damage.
Features
Wide supply voltage range: 3.0V to 15V
High noise immunity: 0.45 VDD (typ.)
Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
Applications
• AND-OR select gating
• Shift-right/shift-left registers
• True/complement selection
• AND/OR/EXCLUSIVE-OR selection
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