资料下载
Verilog Digital System Design
magic_xyc
分享资料个
This book is on the IEEE Standard Hardware Description Language
based on the Verilog® Hardware Description Language (Verilog HDL),
IEEE Std 1364–2001. The intended audiences are engineers involved in
various aspects of digital systems design and manufacturing and students
with the basic knowledge of digital system design. The emphasis of the
book is on using Verilog HDL for the design, verification, and synthesis of
digital systems. We will discuss Register Transfer (RT) level digital system
design, and discuss how Verilog can be used in this design flow.
In the last few years RT level design of digital systems has gone
through significant changes. Beyond simulation and synthesis that are
now part of any RTL design process, we are looking at testbench generation
and automatic verification tools. As with any book on Verilog,
this book covers digital design and Verilog for simulation and synthesis.
However, to ready design engineers for designing, testing, and verifying
large digital system designs, the book contains material for
testbench development and verification. The subjects of testbench and
verification are introduced in Chapter 1. Chapter 2 onwards we concentrate
on Verilog for design and synthesis. This will teach the readers
efficient Verilog coding techniques for describing actual hardware
components. When all of Verilog from a design point of view is presented,
we turn our attention to test and verification. Chapter 6 covers
testbench development techniques and use of assertion verification monitors
for better analysis of a design. Toward the end of the book we put
together our coding techniques for synthesis and testbench development,
and present several RT level designs from design specification to
verification.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
- 相关下载
- 相关文章
