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IEEE 802.16e中LDPC译码器的实现
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格式:rar |
大小:119 |
2009-08-05
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面向IEEE 802.16e 中 LDPC 码，分析了各种译码算法的译码性能，归一化最小（NMS）算法具备较高译码性能和实现复杂度低的特点。提出一种基于部分并行方式的LDPC 译码器结构，可以满足IEEE802.16e 中非规则LDPC 码的译码要求。在FPGA 上实现了该译码器，数据吞吐率可以达到130 Mb/s。
关键词：WiMAX，IEEE 802.16e，LDPC 译码器，部分并行，FPGA
Abstract: In this paper, the decoding performance of decoding algorithms is analyzed for Low
Density Parity Check (LDPC) code of IEEE 802.16e. Normalized Min-Sum(NMS) algorithm
possesses high decoding performance and low complexity. A LDPC decoding architecture based on partially parallel mode is proposed, which can satisfy the demand of irregular LDPC code for IEEE 802.16e. The decoder has been implemented on FPGA，and data throughput reaches 130 Mb/s.
Key Words: WiMAX, IEEE 802.16e, LDPC decoder, partially parallel, FPGA
关键词：WiMAX，IEEE 802.16e，LDPC 译码器，部分并行，FPGA
Abstract: In this paper, the decoding performance of decoding algorithms is analyzed for Low
Density Parity Check (LDPC) code of IEEE 802.16e. Normalized Min-Sum(NMS) algorithm
possesses high decoding performance and low complexity. A LDPC decoding architecture based on partially parallel mode is proposed, which can satisfy the demand of irregular LDPC code for IEEE 802.16e. The decoder has been implemented on FPGA，and data throughput reaches 130 Mb/s.
Key Words: WiMAX, IEEE 802.16e, LDPC decoder, partially parallel, FPGA
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