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74175 TTL带公共时钟和复位四D触发器
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These positive-edge triggered flip-flops utilize TTL circuitry to
implement D-type flip-flop logic. All have a direct clear input,
and the quad (175) version features complementary outputs
from each flip-flop.
Information at the D inputs meeting the setup and hold time
requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse. Clock triggering occurs
at a particular voltage level and is not directly related to
the transition time of the positive-going pulse. When the
clock input is at either the high or low level, the D input signal
has no effect at the output.
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