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DS90C387/DS90CF388,pdf datashe
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2009-10-14
凤毛麟角
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The DS90C387/DS90CF388 transmitter/receiver pair is designed
to support dual pixel data transmission between Host
and Flat Panel Display up to QXGA resolutions. The transmitter
converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL
data into 8 LVDS (Low Voltage Differential Signalling) data
streams. Control signals (VSYNC, HSYNC, DE and two
user-defined signals) are sent during blanking intervals. At a
maximum dual pixel rate of 112MHz, LVDS data line speed is
672Mbps, providing a total throughput of 5.38Gbps (672
Megabytes per second). Two other modes are also supported.
24-bit color data (single pixel) can be clocked into the
transmitter at a maximum rate of 170MHz. In this mode, the
transmitter provides single-to-dual pixel conversion, and the
output LVDS clock rate is 85MHz maximum. The third mode
provides inter-operability with FPD-Link devices.
to support dual pixel data transmission between Host
and Flat Panel Display up to QXGA resolutions. The transmitter
converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL
data into 8 LVDS (Low Voltage Differential Signalling) data
streams. Control signals (VSYNC, HSYNC, DE and two
user-defined signals) are sent during blanking intervals. At a
maximum dual pixel rate of 112MHz, LVDS data line speed is
672Mbps, providing a total throughput of 5.38Gbps (672
Megabytes per second). Two other modes are also supported.
24-bit color data (single pixel) can be clocked into the
transmitter at a maximum rate of 170MHz. In this mode, the
transmitter provides single-to-dual pixel conversion, and the
output LVDS clock rate is 85MHz maximum. The third mode
provides inter-operability with FPD-Link devices.
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