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A DSP Architecture for High-Sp
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2010-06-27
李勇
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This paper presents digital signal processor (DSP)
instructions and their data processing unit (DPU)
architecture for high-speed fast Fourier transforms (FFTs)
in orthogonal frequency division multiplexing (OFDM)
systems. The proposed instructions jointly perform new
operation flows that are more efficient than the operation
flow of the multiply and accumulate (MAC) instruction on
which existing DSP chips heavily depend. We further
propose a DPU architecture that fully supports the
instructions and show that the architecture is two times
faster than existing DSP chips for FFTs. We simulated the
proposed model with a Verilog HDL, performed a logic
synthesis using the 0.35 µm standard cell library, and then
verified the functions thoroughly.
instructions and their data processing unit (DPU)
architecture for high-speed fast Fourier transforms (FFTs)
in orthogonal frequency division multiplexing (OFDM)
systems. The proposed instructions jointly perform new
operation flows that are more efficient than the operation
flow of the multiply and accumulate (MAC) instruction on
which existing DSP chips heavily depend. We further
propose a DPU architecture that fully supports the
instructions and show that the architecture is two times
faster than existing DSP chips for FFTs. We simulated the
proposed model with a Verilog HDL, performed a logic
synthesis using the 0.35 µm standard cell library, and then
verified the functions thoroughly.
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