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SN54AHCT367, SN74AHCT367,pdf(H
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The ’AHCT367 devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE\ and 2OE\) inputs. When OE\ is low, the device passes noninverted data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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