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IC Package Impedance Matching
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2008-09-10
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Impedance Matching Techniques for VLSI Packaging
Problem Statement
•Reflections from interconnect will limit VLSI system performance
•This is caused by :
1) Parasitics of the Package Interconnect
2) Faster Risetimes in Off-chip Driver Circuitry
Agenda
1) Package Interconnect Parasitics
2) Proposed Solution
3) Experimental Results
Why is packaging limiting performance?
•Today’s Package Interconnect Looks Inductive -Long interconnect paths-Large return loops
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