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VHDL Decoder Skeleton
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2009-03-28
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VHDL Decoder Skeleton
Used to Implement the Full CPU Memory Map
The following VHDL code is used as a basis to develop the decoder code required to implement the
full system memory map for the 2BA4 project boards. The code should be entered into a new
project in Xilinx ISE, targeting a XC9572-7PC44 CPLD device. More information on how to compile
the code and upload it to the CPLD target will be provided during the project labs.
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hole1007
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